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Layout-driven Logic Optimization

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Marcadores Sociales
Layout-driven Logic Optimization
Id. 41939740
Idioma inglés
Titulo Layout-driven Logic Optimization
Localización http://citeseer.ist.psu.edu/504195.html
Versión 1.0
Estado Final
Descripción With the advent of deep sub-micron technologies, interconnect loads and delays are becoming dominant. Consequently, the currently used design flow of iteratively performing logic synthesis with statistical wire-load models, doing placement & routing, extracting parasitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the need of the day. A number of researchers have addressed the problem of timing convergence and proposed a variety of solutions ranging from performing logic synthesis with estimates of physical information to combining specific sets of synthesis and physical design steps to postponing synthesis operations to a stage where more accurate physical information is available. However, there is currently no consensus among the design community as to the true solution of the timing convergence problem. Moreover, as designs get larger, designs constraints tighter and cost functions more varied and complicated, the problem is likely to assume even greater importance.
Tipo ps
Palabras clave Layout-driven Logic Optimization
Tipo de Interactividad Expositivo
Nivel de Interactividad muy bajo
Audiencia Estudiante
Profesor
Autor
Estructura Atomic
Coste no
Copyright
unrestricted
Formatos ps
Requerimientos técnicos Browser: Any
Relación [IsBasedOn] http://www.cs.ucla.edu/~apple/PAPERS/date01.ps
[References] oai:CiteSeerPSU:271374
Fecha de contribución 31-mar-2009

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