CONSTRUCTING ONLINE TESTABLE CIRCUITS USING REVERSIBLE LOGIC
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CONSTRUCTING ONLINE TESTABLE CIRCUITS USING REVERSIBLE LOGIC
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| Id. |
45677665 |
| Idioma |
inglés
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| Titulo |
CONSTRUCTING ONLINE TESTABLE CIRCUITS USING REVERSIBLE LOGIC |
| Autor(es) |
Sk Noor Mahammad
Siva Kumar
Sastry Hari
Shyam Shroff
V Kamakoti
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| Localización |
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.101.3387
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| Versión |
1.0 |
| Estado |
Final
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| Descripción |
Testable fault tolerant system design has become vital for many safety critical applications. On the other hand, reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. Any Boolean logic function can be implemented using reversible gates. This paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversible. The resultant reversible testable gate can detect online any single bit errors that include Single Stuck Faults and Single Event Upsets S.Karp et.al (1993). The proposed technique is illustrated using an example that converts a reversible decoder circuit to an online testable reversible decoder circuit.
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| Tipo |
application/pdf
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| Palabras clave |
Reversible Logic
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| Tipo de recurso |
Texto Narrativo
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| Tipo de Interactividad |
Expositivo
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| Nivel de Interactividad |
muy bajo
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| Audiencia |
Estudiante
Profesor
Autor
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| Estructura |
Atomic |
| Coste |
no
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| Copyright |
sí
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Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| Formatos |
application/pdf
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| Requerimientos técnicos |
Browser: Any
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| Relación |
[IsBasedOn] http://www.cs.iitm.ernet.in/~hsiva/papers/219_vdat06.pdf
[References] 10.1.1.52.3274
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| Fecha de contribución |
26-sep-2009 |
| Contacto |
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