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A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model

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A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model
Id. 45700084
Idioma inglés
Titulo A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model
Autor(es) Kuo Chan Huang
Chung Len
Lee
Jwu E Chen
Localización http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.103.5631
Versión 1.0
Estado Final
Descripción This paper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate. It uses Potential-Change Frame, incorporating inertial functions, to execute event-canceling operation of gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it significantly surpasses the conventional time wheel event-driven simulator in terms of simulation speed. In addition, it is also found that a significant percentage (27%) of hazards can be eliminated when the effect of the inertial delay is considered in the simulation.
Tipo application/pdf
Palabras clave logic simulator
Tipo de recurso Texto Narrativo
Tipo de Interactividad Expositivo
Nivel de Interactividad muy bajo
Audiencia Estudiante
Profesor
Autor
Estructura Atomic
Coste no
Copyright
Metadata may be used without restrictions as long as the oai identifier remains attached to it.
Formatos application/pdf
Requerimientos técnicos Browser: Any
Relación [IsBasedOn] http://www.iis.sinica.edu.tw/page/jise/1999/199911_07.pdf
[References] 10.1.1.47.2103
[References] 10.1.1.2.7528
Fecha de contribución 27-sep-2009
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