Logic Synthesis Avoiding State Space Explosion
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Logic Synthesis Avoiding State Space Explosion
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| Id. |
46363591 |
| Idioma |
inglés
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| Titulo |
Logic Synthesis Avoiding State Space Explosion |
| Autor(es) |
V. Khomenko
M. Koutny
Maciej Koutny
A. Yakovlev
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| Localización |
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.8118
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| Versión |
1.0 |
| Estado |
Final
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| Descripción |
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementing each output signal of the circuit. This is usually done using reachability graphs.
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| Tipo |
application/pdf
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| Palabras clave |
logic synthesis
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| Tipo de recurso |
Texto Narrativo
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| Tipo de Interactividad |
Expositivo
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| Nivel de Interactividad |
muy bajo
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| Audiencia |
Estudiante
Profesor
Autor
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| Estructura |
Atomic |
| Coste |
no
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| Copyright |
sí
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Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| Formatos |
application/pdf
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| Requerimientos técnicos |
Browser: Any
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| Relación |
[IsBasedOn] http://www.cs.ncl.ac.uk/research/pubs/trs/papers/813.pdf
[References] 10.1.1.1.5124
[References] 10.1.1.1.9584
[References] 10.1.1.17.8484
[References] 10.1.1.79.9860
[References] 10.1.1.42.8213
[References] 10.1.1.20.9147
[References] 10.1.1.49.2948
[References] 10.1.1.13.7518
[References] 10.1.1.14.2681
[References] 10.1.1.29.6002
[References] 10.1.1.1.6746
[References] 10.1.1.10.6768
[References] 10.1.1.10.4661
[References] 10.1.1.18.9060
[References] 10.1.1.19.4764
[References] 10.1.1.100.9206
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| Fecha de contribución |
24-jul-2009 |
| Contacto |
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