Differential Current Switch Logic: A Low Power DCVS Logic Family
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Differential Current Switch Logic: A Low Power DCVS Logic Family
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| Id. |
46889921 |
| Idioma |
inglés
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| Titulo |
Differential Current Switch Logic: A Low Power DCVS Logic Family |
| Autor(es) |
Dcvs Logic Family
Dinesh Somasekhar
Kaushik Roy
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| Localización |
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.56.2468
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| Versión |
1.0 |
| Estado |
Final
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| Descripción |
A new logic family, Differential Current Switch Logic (DCSL) for implementing clocked CMOS circuits has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1:2¯ MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates, for moderate tree heights. I. Introduction C IRCUIT desig...
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| Tipo |
application/postscript
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| Tipo de recurso |
Texto Narrativo
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| Tipo de Interactividad |
Expositivo
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| Nivel de Interactividad |
muy bajo
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| Audiencia |
Estudiante
Profesor
Autor
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| Estructura |
Atomic |
| Coste |
no
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| Copyright |
sí
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Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| Formatos |
application/postscript
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| Requerimientos técnicos |
Browser: Any
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| Relación |
[IsBasedOn] http://www.ece.purdue.edu/~vlsi/papers/Dinesh/jssc-paper.ps
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| Fecha de contribución |
13-ago-2009 |
| Contacto |
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