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This paper addresses the problem of generating robust tests (tests which are efficient even in the presence of arbitrary delays) for stuck-open faults, in CMOS logic networks. The authors' approach consists of a topological analysis leading to the definition of a criterion which allows them to distinguish between robustly and non-robustly testable gates. They also present a new design for testability method, to be applied to non-robustly testable gates.

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Darlay , F. -  Courtois , B. - 

Id.: 71313760

Idioma: inglés  - 

Versión: 1.0

Estado: Final

Palabras clavePACS 85.42 - 

Tipo de recurso: info:eu-repo/semantics/conferenceObject  -  Conference papers  - 

Tipo de Interactividad: Expositivo

Nivel de Interactividad: muy bajo

Audiencia: Estudiante  -  Profesor  -  Autor  - 

Estructura: Atomic

Coste: no

Copyright: sí

Requerimientos técnicos:  Browser: Any - 

Relación: [IsBasedOn] EDAC.-Proceedings-of-the-European-Design-Automation-Conference.
[IsBasedOn] https://hal.archives-ouvertes.fr/hal-00007780
[IsBasedOn] 1990, IEEE Comput. Soc. Press, Washington, DC, USA, pp.344-9, 1990

Fecha de contribución: 17-may-2018


* hal-00007780

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