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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of FPGAS as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various FPGA co-processor arrangements.

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Faculty of Technology ePrints Service  


Howard, Neil J. -  Tyrrell, Andrew M. -  Allinson, Nigel M. - 

Id.: 55211150

Idioma: inglés  - 

Versión: 1.0

Estado: Final

Tipo:  application/pdf - 

Palabras claveG730 Neural Computing - 

Tipo de recurso: Article  -  PeerReviewed  - 

Tipo de Interactividad: Expositivo

Nivel de Interactividad: muy bajo

Audiencia: Estudiante  -  Profesor  -  Autor  - 

Estructura: Atomic

Coste: no

Copyright: sí

Formatos:  application/pdf - 

Requerimientos técnicos:  Browser: Any - 

Relación: [References] http://eprints.lincoln.ac.uk/5029/
[References] http://www.hindawi.com/journals/vlsi/1996/017505/abs/
[References] 10.1155/1996/17505

Fecha de contribución: 30-may-2014


* Howard, Neil J. and Tyrrell, Andrew M. and Allinson, Nigel M. (1996) The use of field-programmable gate arrays for the hardware acceleration of design automation tasks. VLSI Design, 4 (2). pp. 135-139. ISSN 1065-514X

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