1.
Digital signal processing: the impact of convergence on education, society and design flow - Appiah, Kofi; Andrew, Hunter
Design and development of real-time, memory and processor hungry digital signal processing systems has for decades been accomplished on general-purpose microprocessors. Increasing needs for high-performance DSP systems made these microprocessors unattractive for such implementations. Various attempts to improve the performance of these systems resulted in the use of dedicated digital signal processing devices like DSP processors and the former heavyweight champion of electronics design – Application Specific Integrated Circuits.
The advent of RAM-based Field Programmable Gate Arrays has changed the DSP design flow. Software algorithmic designers can now take their DSP algorithms right from inception to hardware implementation, thanks to...
2.
An FPGA-based infant monitoring system - Dickinson, Patrick; Appiah, Kofi; Hunter, Andrew; Ormston, Stephen
We have designed an automated visual surveillance system for monitoring sleeping infants. The low-level image
processing is implemented on an embedded Xilinx’s Virtex
II XC2v6000 FPGA and quantifies the level of scene activity using a specially designed background subtraction algorithm. We present our algorithm and show how we have
optimised it for this platform.
3.
GW4: An FPGA-driven image segmentation algorithm - Appiah, Kofi; Hunter, Andrew; Kluge, Tino
We describe “GW4,” an efficient video segmentation algorithm designed for FPGA implementation. The algorithm detects moving foreground objects against a multimodal background; it is motivated by two well-known adaptive background differencing algorithms, Grimson's algorithm and W4. GW4 is designed specifically for implementation on reconfigurable FPGA hardware, avoiding the use of floating point numbers and transcendental operations, and operates at real-time frame rates on 640x480 video streams. We present experimental results indicating processing speeds, and superior segmentation performance to Grimson's algorithm.
4.
A single-chip FPGA implementation of real-time adaptive background model - Appiah, Kofi; Hunter, Andrew
This paper demonstrates the use of a single-chip
FPGA for the extraction of highly accurate background
models in real-time. The models are based
on 24-bit RGB values and 8-bit grayscale intensity
values. Three background models are presented, all
using a camcorder, single FPGA chip, four blocks
of RAM and a display unit. The architectures have
been implemented and tested using a Panasonic NVDS60B
digital video camera connected to a Celoxica
RC300 Prototyping Platform with a Xilinx Virtex
II XC2v6000 FPGA and 4 banks of onboard RAM.
The novel FPGA architecture presented has the advantages
of minimizing latency and the movement of
large datasets, by conducting time critical processes
on BlockRAM. The systems operate at...
5.
FPGA applications in signal and image processing - Appiah, Kofi E
The increasing demand for real-time and smart digital signal processing (DSP) systems, calls for a better platform for their implementation. Most of these systems (e.g. digital image processing) are highly parallelisable, memory and processor hungry; such that the increasing performance of todayâs general-purpose microprocessors are no longer able to handle them. A highly parallel hardware architecture, which offers enough memory resources, offers an alternative for such DSP implementations.
6.
An intelligent reconfigurable infant monitoring system - Appiah, Kofi; Dickinson, Patrick; Hunter, Andrew
We have devised an automated visual surveillance system for monitoring sleeping infants. The system architecture requires that low-level image processing is executed on camera by an embedded signal processing unit: thus in tegrating more functionality into a single chip and realising lower product cost. The processing unit quantifies the level of scene activity using a specially designed background subtraction algorithm. In this paper we begin by describing the overall structure of our system. We proceed by present ing our algorithms, and demonstrating their effectiveness in measuring scene activity. We conclude by describing the FPGA-based low-level processing functions, and show how...
7.
GW4: a real-time background subtraction and maintenance algorithm for FPGA implementation - Appiah, Kofi; Hunter, Andrew; Kluge, Tino
GW4 is a real-time video segmentation algorithm for detecting moving objects in indoor and outdoor scenes. The platform for the final implementation is Field Programmable Gate Array (FPGA); a reconfigurable computing platform. The algorithm detects moving foreground objects against a multimodal background; it is motivated by two well-known adaptive background differencing algorithms: Grimson's algorithm and W4. The implementation is based on a single stationary camera transmitting RGB values at 25Hz. Background modelling at pixel level has been used in many applications, but may fail due to camouflage and foreground aperture problems. These common problems have been reduced in our approach...
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