Recursos de colección
Caltech Authors (165.044 recursos)
Repository of works by Caltech published authors.
Group = Computer Science Technical Reports
Repository of works by Caltech published authors.
Group = Computer Science Technical Reports
Keller, Sean; Bhargav, Siddharth S.; Moore, Chris; Martin, Alain J.
In order to build energy efficient digital CMOS circuits, the supply voltage must be reduced to near-threshold.
Problematically, due to random parameter variation, supply
scaling reduces circuit robustness to noise. Moreover, the effects of parameter variation worsen as device dimensions diminish, further reducing robustness, and making parameter variation one of the most significant hurdles to continued CMOS scaling. This paper presents a new metric to quantify circuit robustness with respect to variation and noise along with an efficient method of calculation. The method relies on the statistical analysis of standard cells and memories resulting an an extremely compact representation of robustness data....
Martin, Alain J.
The semantics of a pair of synchronization primitives is characterized by three fundamental axioms: boundedness, progress, and fairness. The class of primitives fulfilling the three axioms is semantically defined. Unbuffered communication primitives, the symmetrical P and V operations, and the usual P and V operations are proved to be the three instances of this class. The definitions obtained are used to prove a series of basic
theorems on mutual exclusion, producer-consumer coupling, deadlock, and linear and circular arrangements of communicating buffer-processes. An implementation of P and V operations fulfilling the axioms is proposed.
Martin, Alain J.
Twenty-five years ago, in December 1988, my
research group at Caltech submitted the world’s
first asynchronous (“clockless”) microprocessor
design for fabrication to MOSIS. We received
the chips in early 1989; testing started in February 1989. The chips were found fully functional on first silicon. The results were presented at the Decennial Caltech VLSI Conference in March of the same year. The first entirely
asynchronous microprocessor had been designed
and successfully fabricated. As the technology finally reaches industry, and with the benefit of a
quarter-century hindsight, here is a recollection
of this landmark project.
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Johnsson, Lennart; Cohen, Danny
This paper proposes a mathematical formalism for the synthesis and qualitative analysis of computational networks that treats data and control in the same manner. Expressions in this notation are given a direct interpretation in the implementation domain. Topology,
broadcasting, pipelining, and similar properties of implementations can be determined directly from the expressions.
This treatment of computational networks emphasizes the space/time tradeoff of implementations. A full instantiation in space of most computational problems is unrealistic, even in VLSI (Finnegan [4]). Therefore, computations also have to be at least partially
instantiated in the time domain, requiring the use of explicit control mechanisms, which typically cause...
Kajiya, James Thomas
A new technique for the modelling of perceptual
systems called formal modelling is developed. This
technique begins with qualitative observations about the
perceptual system, the so-called perceptual symmetries, to
obtain through mathematical analysis certain model
structures which may then be calibrated by experiment.
The analysis proceeds in two different ways depending upon
the choice of linear or nonlinear models. For the linear
case, the analysis proceeds through the methods of unitary
representation theory. It begins with a unitary group
representation on the image space and produces what we
have called the fundamental structure theorem. For the
nonlinear case, the analysis makes essential use of
infinite-dimensional manifold theory. It begins with a
Lie group action...
Trimberger, Stephen
N/A
Martin, A. J.
A method is described for implementing on a finite network of processing "cells", called the "implementation graph", programs whose potential parallelism is not fixed by the implementation but varies according to the input parameters. First, programming constructs are described
permitting a computation, regarded as a dynamic structure called the "computation graph", to diffuse through the implementation graph. Second, the implementation problem of
mapping an unbounded number of computation nodes on a finite number of cells is tackled. Processor allocation and message buffering completely disappear from the programmer's concerns. The mechanism proposed is considered a generalization of the stack mechanism.
Johnsson, Lennart
Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large
number of processors on a single chip will be possible. The cost of communication will make
designs enforcing locality superior to other types of designs.
Scaling down feature sizes results in increase of the delay that wires introduce. The delay even...
Sutherland, Ivan E.
The memoranda listed below describe the polygon package in
its present state. For easy reference, these memoranda have
been packaged together.
Some of the material included is obsolete. In general, the
later-dated material is better than the earlier material.
Some specific hazards are indi~ated in the index below.
Li, Pey-yun Peggy
The tree machine has been well defined as a concurrent computing system by Sally Browning & Carver Mead [1]. Many algorithms have been developed and shown to have better time-performance than conventional sequential algorithms. And since a tree machine is being built and is expected to become operational within a year, a real tree machine (not just a mathematical model or some pieces of hardware) is about to face the world. This report is treating the bridging between the mathematical model and the hardware machine to make the Tree Machine become real!
In the following sections, I will describe the hardware...
Tarolli, Gary M.
[No abstract]
Henisz Thompson, Bozena; Thompson, Frederick B.
A major thrust of artificial intelligence research is how to build knowledge of the application domain into computer systems. We investigate how the user himself can introduce his own expert knowledge into his data base language extension so that it may then respond intelligently to his curt queries and commands. Illustrations of rapid language extension using the REL System are presented and discussed.
Johannsen, Dave
Advances in LSI technology allow the system designer to implement large amounts of processing capability on a single silicon chip. It will soon be possible to construct a large number of processing elements on these chips. How will the system designer organize these processing elements? Hierarchically designed array or tree machines arc two possible alternatives. This paper provides a background for study of array and tree machines by examining how to supply power to an array of processing elements.
Mahowald, Misha
This thesis describes the development and testing of a simple visual system fabricated using complementary metal-oxide-semiconductor (CMOS) very large scale integration (VLSI) technology. This visual system is composed of three subsystems. A silicon retina, fabricated on a single chip, transduces light and performs signal processing in a manner similar to a simple vertebrate retina. A stereocorrespondence chip uses bilateral retinal input to estimate the location of objects in depth. A silicon optic nerve allows communication between chips by a method that preserves the idiom of action potential transmission in the nervous system. Each of these subsystems illuminates various aspects of...
Lang, Dick
LAP is a set of Simula procedures and objects declared externally for use in generating CIT 2.0. The user can use these procedures and any other Simula statements to programmatically generate chip geometry.
Trimberger, Stephen
Layout languages provide users with the capability to algorithmically define cells. But the specification language is so non-intuitive that it is impossible to debug a
design in that language, one must plot it. Interactive graphics systems, on the other hand, allow the user to debug in the form in which he sees the design, but severely
restrict the language he may use to express the graphics. For example, he cannot express loops or conditionals. What is really needed is a single interactive system
that combines layout language and graphic modifications to the data. This paper describes just such a system.
Trimberger, Stephen
This is version 1.0 of the Sticks Standard. Software has been written to interface this standard to plotters, a graphic Sticks editor, a Stick compactor and several
simulators. The Standard appears adequate to describe cells for chip assemblers as well as Stick diagram editing and compaction systems. However, this version of the
Sticks Standard cannot efficiently describe large chips because it lacks an array facility. This deficiency will be corrected in the next release of the Sticks Standard:
This document consists of four parts: Sticks definition, Sticks Standard design considerations, the specification of the Sticks Standard, and an example of the Standard in...
Trimberger, Stephen
No abstract.