Mostrando recursos 121 - 140 de 10.867

  1. Design of a GaAs redundant divider

    Moussa , I.; Skaf , A.; Guyot , A.
    Presents a fast combinatorial circuit for performing division Q:=A+D. High speed is achieved by a new algorithm implemented in gallium arsenide (GaAs). An n bit divider produces an n bit quotient Q in 9*n NOR-gate-delay-units, with n/sup 2/ add/sub cells (called tail) driven by n controller cells (called head). The divider has been implemented by using a buffering technique and a full custom layout methodology, which are well suited for high performance design in GaAs direct coupled FET Logic (DCFL).

  2. Logic synthesis for automatic layout

    Abouzeid , P.; Leveugle , R.; Saucier , G.
    This paper presents an attempt to automate the design of modules using a synthesis tool aimed at complex CMOS cells implementation. The synthesis process is described and a gain of 32% in terms of transistors and number of cells, compared with a standard cell implementation, is reported.

  3. Logic synthesis for automatic layout

    Abouzeid , P.; Leveugle , R.; Saucier , G.; Jamier , R.
    ISBN: 0818628456

  4. ASYL: a logic and architecture design automation system

    Crastes-De-Paulet , M.; Duff , C.; Leveugle , R.; Poirot , F.; Saucier , G.; Sicard , P.
    This paper is focused on the ASYL system with a special emphasis on the four most original aspects which are the 2-level minimization, the multi-level synthesis on PALs, the multi-level synthesis on compiled cells, and the state assignment of controllers. The ASYL system which is dedicated to synthesis is coupled with the CADOC system. CADOC which has been developed in the framework of an ESPRIT Project, is dedicated to functional simulation and is used as a high-level input-language and as a simulator. Results for the different topics are presented on classical international benchmarks.

  5. Architecture study and design of mixed circuits using asynchronous logic: Application to very low power consumption and contactless systems

    Caucheteux , D.
    ISBN 2-84813-080-6

  6. A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

    Herve , C.; Torki , K.
    This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of < plus-or-minus sign >0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 mu m BiCMOS technology. Time...

  7. Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logic

    Morin-Allory , K.; Cachera , David
    International audience

  8. A programmable logic architecture for prototyping clockless circuits

    Fesquet , Laurent; Renaudin , Marc
    ISBN: 0-7803-9362-7

  9. Asynchronous Systems on Programmable Logic

    Fesquet , Laurent; Quartana , J.; Renaudin , Marc
    ISBN 2-9517-4611-3

  10. Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic

    Monnet , Y.; Renaudin , Marc; Leveugle , R.
    ISSN: 0018-9340

  11. Design for soft error mitigation

    Nicolaidis , M.
    In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern for space applications in the past, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEU), affecting memory cells, latches, and flip-flops, and single-event transients (SET), initiated in the combinational logic and captured by the latches and flip-flops associated to the outputs of this logic. To face this challenge, a designer must dispose a variety of soft error mitigation schemes adapted to various circuit structures, design architectures, and design constraints. In this paper, we describe various SEU and...

  12. State-holding in Look-Up Tables: application to asynchronous logic

    Fesquet , Laurent; Folco , Bertrand; Steiner , M.; Renaudin , Marc
    3-901882-19-7

  13. Towards a formal theory of communication architecture in the ACL2 logic

    Schmaltz , J.; Borrione , D.
    International audience

  14. CNTFET-based logic gates and simulation

    Dang , T.; Anghel , L.; Leveugle , R.
    International audience

  15. Clockless circuits and systems

    Renaudin , Marc
    Clock-less or asynchronous circuits are getting more and more importance in the industry today. Very recently, ARM disclosed a partnership with Handshake Solutions to design an ARM clockless core, Silistix announced CHAIN a self timed packet based network on chip, Fulcrum Microsystems is sampling the FocalPoint family chips, Achronix is announcing 1GHz and 2GHz clock less FPGAs, and most of the main actors in the semi conductor industry are studying the potentials of clock less circuits. Even if there is still a lot to do, especially in the domain of CAD tools, and even if asynchronous logic is still a...

  16. CNTFET-based logic gates and characteristics

    Dang , T.; Anghel , L.; Leveugle , R.
    International audience

  17. FPGA Architecture for Multi-Style Asynchronous Logic

    Huot , N.; Dubreuil , H.; Fesquet , Laurent; Renaudin , Marc
    Submitted on behalf of EDAA (http://www.edaa.com/)

  18. Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies

    Anghel , L.; Nicolaidis , M.
    In future nanotechnologies failure densities are predicted to be several orders of magnitude higher than in current CMOS technologies. For such failure densities existing fault tolerance implementations are inadequate. This work presents several principles of building multiple-fault tolerant memory cells and logic gates for circuits affected by high defect densities as well as a first evaluation of the area cost and performance.

  19. Cost Reduction and Evaluation of a Temporary Faults Detecting Technique

    Anghel , L.; Nicolaidis , M.
    IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result on unacceptable rates of soft-errors. Furthermore, defect behavior is becoming increasingly complex resulting on increasing number of timing faults that can escape detection by fabrication testing. Thus, fault tolerant techniques will become necessary even for commodity applications. This work considers the implementation and improvements of a new soft error and timing error detecting technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the...

  20. Un nouveau regard sur la machine logique de Jevons

    Amblard , P.
    Jevons's Logic Piano has already been presented in several publications. It was the first hardware devoted to logical inference. In this paper we propose a new view of that machine in the frame of Finite States Machines. Indeed Jevons's Logical Machine is a set of finite states transducers with a Single Instruction Multiple Data organization. This allows it to evaluate some boolean formulas with N variables in space proportional to 2N and in constant time.

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