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Nomenclatura Unesco > (11) Lógica

Mostrando recursos 161 - 180 de 132,301

161. Adaptive Error-Prediction Aging Sensor for On-Line Monitoring of Performance Errors - C. V. Martins; J. Pachito; J. Semião; I. C. Teixeira; J. P. Teixeira
Abstract—This paper presents a new aging sensor architecture for error prediction of performance errors in synchronous digital circuits. The aging sensor is based on a new flip-flop with built-in logic that predicts the errors by monitoring long-term performance degradation of CMOS digital systems. The main advantage is that the sensor’s long-term degradation effects increase its sensitivity to performance error prediction. Moreover, the reduction of the power-supply voltage (V) and the increase of the temperature (T) also make the sensor to increase its sensitivity, making the sensor to adapt its monitoring capability with aging and VT variations. Performance failure prediction is...

162. Access control with IBM tivoli access manager - G ¨unter Karjoth
Web presence has become a key consideration for the majority of companies and other organizations. Besides being an essential information delivery tool, the Web is increasingly being regarded as an extension of the organization itself, directly integrated with its operating processes. As this transformation takes place, security grows in importance. IBM Tivoli Access Manager offers a shared infrastructure for authentication and access management, technologies that have begun to emerge in the commercial marketplace. This paper describes the Authorization Service provided by IBM Tivoli Access Manager for e-business (AM) and its use by AM family members as well as third-party applications....

163. General Terms - César García-osorio; Carlos Gómez Palacios; Nicolás García-pedrajas
In this paper we present a tool to assist in teaching top-down and bottom-up analysis algorithms. The tool provides simu-lation for the following analysis algorithms: LL, SLR, LALR and LR. During the simulation the student can simultane-ously see the pending input, the analysis stack and tables, the generated output and the parse tree. Categories and Subject Descriptors F.4.2 [Mathematical Logic and Formal Languages]: Grammars and other Rewriting Systems—grammar type, parsing

164. The logic of organizational markets: Thinking through resource partitioning theory - Ivar Vermeulen; Jeroen Bruggeman
Resource partitioning theory claims that “Increasing concentration enhances the life chances of specialist organizations. ” We systemati-cally think through this theory, specify implicit background assump-tions, sharpen concepts, and rigorously check the theory’s logic. As a result, we increase the theory’s explanatory power, and claim— contrary to received opinion—that under certain general conditions, “resource partitioning ” and the proliferation of specialists can take place independently of organizational mass and relative size effects, size localized competition, diversifying consumer tastes, increasing number of dimensions of the resource space, and changing niche widths. Our analysis makes furthermore clear that specialist and generalist strategies are...

165. Design and development of a REST-based Web service platform for applications integration By - Luis Oliva Felipe
Web services have attracted attention as a possible solution to share knowledge and application logic among different heterogeneous agents. A classic approach to this subject is using SOAP, a W3C protocol aimed to exchange structured information. The Web Services Interoperability organization (WS-I), defines a set of extensions, commonly called WS-*, which further enhance this knowledge exchange defining mechanisms and functionalities such as security, addressability or service composition. This thesis explores a relatively new alternative approach to the SOAP/WS-I stack: REST-based Web services. The acronym REST stands for Representational state transfer; this basically means that each unique URL is a representation...

166. 1Logic-Based Distributed Routing for NoCs - Jose ́ Flich; Jose ́ Duato
Abstract—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are usually proposed for NoCs, hetero-geneous cores, manufacturing defects, hard failures, and chip virtualization may lead to irregular topologies. In this context, efficient routing becomes a challenge. Although switches can be easily configured to support most routing algorithms and topologies by using routing tables, this solution does not scale in terms of latency and area. We propose a new circuit that removes the need for using routing tables. The new mechanism, referred to...

167. Equivalences in answer-set programming by countermodels in the logic of here-and-there - Michael Fink
Abstract. In Answer-Set Programming different notions of equivalence, such as the prominent notions of strong and uniform equivalence, have been studied and characterized by various selections of models in the logic of Here-and-There (HT). For uniform equivalence however, correct characterizations in terms of HT-models can only be obtained for finite theories, respectively programs. In this paper, we show that a selection of countermodels in HT captures uniform equiva-lence also for infinite theories. This result is turned into coherent characterizations of the different notions of equivalence by countermodels, as well as by a mixture of HT-models and countermodels (so-called equivalence interpretations),...

168. by - Tihomir Surdilovic; Tihomir Surdilovic
ii People with severe motor-impairments due to Spinal Cord Injury (SCI) or Spinal Cord Dysfunction (SCD), often experience difficulty with accurate and efficient control of pointing devices (Keates et al., 02). Usually this leads to their limited integration to society as well as limited unassisted control over the environment. The questions “How can someone with severe motor-impairments perform mouse pointer control as accurately and efficiently as an able-bodied person? ” and “How can these interactions be advanced through use of Computational Intelligence (CI)? ” are the driving forces behind the research described in this paper. Through this research, a novel...

169. Design Assembly Techniques for FPGA BackEnd Acceleration - Tannous Frangieh; Carl B. Dietrich; Wu-chun Feng; Brent E. Nelson; Patrick R. Schaumont; Tannous Frangieh
Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows. Dedication I lovingly dedicate this work to my father, mother, sister and two brothers. iii...

170. Understanding and Assessing Logic Control Design Methodologies - Morrison Ray Lucas
I would like to acknowledge the Engineering Research Center for Reconfigurable Ma-chining Systems (ERC/RMS) for providing the inspiration and direction for much of this work. This would not have been possible without the support of the National Science Foundation under grant EEC95-29125, which supported the ERC/RMS and me throughout my graduate career. I would also like to thank my advisor, Professor Dawn M. Tilbury, for her advice and direction throughout my graduate career. Finally, I would like to thank the industrial members of the ERC/RMS for their explanations of “real world ” problems. I would especially like to thank Ruven...

171. DIGITAL FILTERS SYNTHESIZED USING THE FRM TECHNIQUE* - Yong Ching Lim; Ya Jun Yu; Huan Qun Zheng; Say Wei Foo
Abstract. The effective length of a filter designed using the frequency-response masking (FRM) technique is very long and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the field programmable gate array (FPGA) and external memory when the random logic is implemented using the FPGA and the delay elements are implemented using an external memory such as dynamic random access memory. Key words: Digital filters, FIR filters, FRM technique. 1.

172. Categorical Abstract Algebraic Logic: Partially Ordered Algebraic Systems - George Voutsadakis; To Don Pigozzi; Kate Pa =lasińska
Abstract. An extension of parts of the theory of partially ordered varieties and quasivarieties, as presented by Paaasińska and Pigozzi in the framework of abstract algebraic logic, is developed in the more abstract framework of categorical abstract algebraic logic. Algebraic systems, as introduced in previous work by the author, play in this more abstract framework the role that universal algebras play in the more traditional treatment. The aim here is to build the generalized framework and to formulate and prove abstract versions of the ordered homomorphism theorems in this framework.

173. A View of Costed Pi-calculus for Particle Swarm Optimization with QoS-aware Service Selection ★ - Desheng Li; Bo Cheng; Na Deng; Changbao Li; Junliang Chen; Chuanchang Liu
This paper presents a novel computation model for Particle Swarm Optimization (PSO) based on process algebras, which consists of some additional primitives, such as beam channel, logic parallels, logic choices, cost, cost choices and so forth. In this calculus, everything is a cost expression including the cost of a expression, the choice of expressions, or even the search procedure of PSO itself. As an instance of the applications using discrete PSO, QoS-aware web service selection can be modeled naturally in this calculus and the algebraic and physical representation of the solution is imported to guideline the design of discrete scheme...

174. Search engines for the World Wide Web: a comparative study and evaluation methodology. ASIS. From http://www.asis.org/annual96/Electronic-Proceedings/chu.htm 664 - Heting Chu; Marilyn Rosenthal
Three Web search engines, namely, Alta Vista, Excite, and Lycos, were compared and evaluated in terms of their search capabilities (e.g., Boolean logic, truncation, field search, word and phrase search) and retrieval performances (i.e., precision and response time) using sample queries drawn from real reference questions. Recall, the other evaluation criterion of information retrieval, is deliberately omitted from this study because it is impossible to assume how many relevant items there are for a particular query in the huge and ever changing Web system. The authors of this study found that Alta Vista outperformed Excite and Lycos in both search...

175. An Abstract Decision Procedure for Satisability in the Theory of Recursive Data Types - Clark Barrett; Igor Shikanian; Cesare Tinelli
The theory of recursive data types is a valuable modeling tool for software verication. In the past, decision procedures have been proposed for both the full theory and its universal fragment. However, previous work has been limited in various ways, including an inability to deal with multiple constructors, multi-sorted logic, and mutually recursive data types. More signicantly, previous algorithms for the universal case have been based on ineÆcient nondeterministic guesses and have been described in fairly complex procedural terms. We present an algorithm which addresses these issues for the universal theory. The algorithm is presented declaratively as a set of...

176. Viewing λ-terms through Maps - Masahiko Sato; Randy Pollack; Takafumi Sakurai
In this paper we introduce the notion of map, which is a notation for the set of occurrences of a symbol in a syntactic expression such as a formula or a λ term. We use binary trees over 0 and 1 as maps, but some well-formedness conditions are required. We develop a representation of lambda terms using maps. The representation is concrete (inductively definable in HOL or Constructive Type Theory) and canonical (one representative per λ term). We define substitu-tion for our map representation, and prove the representation is in substitution preserving isomorphism with both nominal logic λ terms and...

177. $rec.titulo - Alexandru Baltag; Lawrence S. Moss
ABSTRACT. We construct logical languages which allow one to represent a variety of possible types of changes affecting the information states of agents in a multi-agent setting. We formalize these changes by defining a notion of epistemic program. The languages are two-sorted sets that contain not only sentences but also actions or programs. This is as in dynamic logic, and indeed our languages are not significantly more complicated than dynamic logics. But the semantics is more complicated. In general, the semantics of an epistemic program is what we call a program model. This is a Kripke model of ‘actions’, representing...

178. $rec.titulo
The development of a quantum computer based on a system of trapped atomic ions is described, following the proposal of Cirac and Zoller. Initial results on a two-bit quantum logic gate are pres-ented, and select experimental issues in scaling the system to larger numbers of ions and gates are treated.

179. NetFPGA Logic Analyzer - Andrew Goodney; Shailesh Narayan; Mengchen Wang; Peigen Sun; Vivek Bh; Young H. Cho
The NetFPGA network interface card provides a platform for deploying reconfigurable hardware in the network. Researchers are able to build and simulate a design within an integrated design environment; however debugging a design on the NetFPGA itself is non-trivial. Furthermore, manually creating signals and input data for a simulation that accurately represents a real network data flow is difficult. In this paper we present a NetFPGA Logic Analyzer with a triggering mechanism that captures the control signals and data path of the NetFPGA at the full 125M samples per second for the allotted duration. The triggering mechanism is a programmable...

180. Some, “Detailed Radiation Fault Modeling of the Remote Exploration and Experimentation - John Beahan; Larry Edmonds; Robert D. Ferraro; Allan Johnston; Daniel S. Katz; Raphael R. Some
Abstract--The goal of the NASA HPCC Remote Exploration and Experimentation (REE) Project is to transfer commercial supercomputing technology into space. The project will use state of the art, low-power, non-radiation-hardened, Commercial Off-The-Shelf (COTS) hardware chips and COTS software to the maximum extent possible, and will rely on Software-Implemented Fault Tolerance (SIFT) to provide the required levels of availability and reliability. In this paper, we outline the methodology used to develop a detailed radiation fault model for the REE Testbed architecture. The model addresses the effects of energetic protons and heavy ions which cause Single Event Upset (SEU) and Single Event...

 

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