Mostrando recursos 41 - 60 de 171,856

  1. Simulation and Synthesis of Majority Logic Decoder/Detector for EG-LDPC Codes

    Rajampet Kadapa; Rajampet Kadapa; V. Usha Sree; Ph. D; Head Of Dept
    In this paper, a technique was proposed to protect memory cells, which are more susceptible to soft errors. These memory cells are to be protected with effective error correction codes. MLD codes are suitable for memory applications because of their ability to correct large number of errors. Conversely, they increase the average latency of the decoding process because it depends upon the code size that impacts memory performance. A method was proposed as majority logic decoder/detector of Euclidean geometry low density parity check codes(EG-LDPC).BUT this MLDD reduces the decoding time, memory access time and area utilization. In this brief, we...

  2. Feedbacks on Future Internet Vision and Design Principles


    At the end of January, the FIArch WG released a new report describing the “Future Internet Design Principles ” [FIArch12]. SOFI EU Project also contributed to this work, mainly for the “seeds ” (see below) called “Resource awareness ” and “Dependability logic”. The contents of this report were presented in Brussels in an open workshop on February 22nd 2012. About forty people participated to the event and discussed the content of this important result of the FIArch WG. During the workshop it has been also distributed a questionnaire to all the participants to collect feedbacks on their vision of what...

  3. A Vernacular for Coherent Logic?

    Julien Narboux; Marc Bezem
    Abstract. We propose a simple, yet expressive proof representation from which proofs for different proof assistants can easily be generated. The representation uses only a few inference rules and is based on a frag-ment of first-order logic called coherent logic. Coherent logic has been recognized by a number of researchers as a suitable logic for many ev-eryday mathematical developments. The proposed proof representation is accompanied by a corresponding XML format and by a suite of XSL transformations for generating formal proofs for Isabelle/Isar and Coq, as well as proofs expressed in a natural language form (formatted in LATEX or in...

  4. IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS 1 Generation of Single Input Change Test Sequences for Conformance Test of Programmable Logic Controllers

    Julien Provost; Jean-marc Roussel; Jean-marc Faure
    Abstract—Conformance test is a functional test technique which is aiming to check whether an implementation, seen as a black-box with inputs/outputs, conforms to its specification. Numerous theoretical worthwhile results have been obtained in the domain of conformance test of finite state machines. The optimization criterion which is usually selected to build the test sequence is the minimum-length criterion. Based on experimental results, this paper focuses on the generation of a Single Input Change (SIC) test sequence from a specification model represented as a Mealy machine; such a sequence is aiming at preventing from erroneous test verdicts due to incorrect detection...

  5. Trade Policy Lobbying in the European Union: Who Captures Whom,’ in

    Cornelia Woll
    forthcoming. I would like to thank Holger Döring and Armin Schäfer for their helpful remarks. What role do firms play in the making of EU trade policy? This article surveys the policy domain and lays out the instruments firms can employ to influence decisions on trade. It underlines that European trade policy is characterized by a high degree of institutional complexity, which firms have to manage in order to be successful. In particular, the European Commission works intensively to solicit business input in order to gain bargaining leverage vis-à-vis third countries and the EU member states. This reverse lobbying creates...

  6. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <


    Abstract — This paper describes a project to create a novel design and simulation tool for quantum-dot cellular automata (QCA), namely QCADesigner. QCA logic and circuit designers require a rapid and accurate simulation and design layout tool to determine the functionality of QCA circuits. QCADesigner gives the designer the ability to quickly layout a QCA design by providing an extensive set of CAD tools. As well, several simulation engines facilitate rapid and accurate simulation. This tool has already been used to design full-adders, barrel shifters, random-access memories, etc. These verified layouts provide motivation to continue efforts toward final implementation of...

  7. On labeled birooted tree languages: algebras, automata

    David Janin; Université De Bordeaux
    and logic

  8. Intersection and Union Logic

    Simona Ronchi; Della Rocca; Alexis Saurin; Yiorgos Stavrinos; Anastasia Veneti
    In [7] and [5, 6] the authors defined “Intersection Logic ” IL and “Intersection Synchronous Logic” ISL, respectively, aiming to give a logical account of intersection types [2]. The problem of a logical foundation of intersection types has been proposed by Hindley [4] as a consequence of the observation that the intersection connective does not coincide with the intuitionistic conjunction. ISL is a deductive

  9. A Genetic-Fuzzy Algorithm for Load Balancing in Multiprocessor Systems

    Roya Nourzadeh; Mehdi Effatparvar
    With the increasing use of computers in research contributions, added requirement for faster processing is now an important necessity. Parallel Processing describes the concept of running tasks which can be run simultaneously on several processors. Load balancing is very important problem in multiprocessor systems. In this paper, we introduce a approah based on Genetic Algorithms and Fuzzy Logic for laod balancing in parallel multiprocessor systems that call GAF algorithm. Extensive simulation shows our algorithm is better than other approach. Simualation results indicate our algorithm have maximum utilization and it reduce total response time of system.

  10. DOI 10.1007/s11787-013-0082-0 Logica Universalis Deduction as Reduction, from a Categorical Point of View

    Dominique Duval
    Abstract. Deduction systems and graph transformation systems are com-pared within a common categorical framework. This comparison results in a proposal for a new deduction method in diagrammatic logics, allowing the deletion of intermediate lemmas. Mathematics Subject Classification (2010). 03G27, 18C30.

  11. SEEING –ACTING – SPEAKING IN GEOMETRY: A CASE STUDY

    Thomas Barrier; Christophe Hache; Anne-cécile Mathé
    The purpose of this paper is to describe and analyse the confrontation and changing processes of frequentation modes (seeing – acting – speaking) of 1st grade secondary school students (10-11 years old) during two geometric construction tasks. This work is based on a logic analysis of the mathematical concepts involved: the midpoint of a line segment and the circle.

  12. CHAPTER 5 SOLID-STATE TRANSMITTERS

    Michael T. Borkowski
    Solid-state devices have largely superseded vacuum tubes in logic and other low-power circuits and even in some very high power applications such as power sup-plies and power converters below 1 MHz. The only exception seems to be cathode-ray tubes (CRTs), which are less costly than large plasma displays. In

  13. Gradual Classical Logic for Attributed Objects

    Ryuta Arisaka
    Abstract—‘There is knowledge. There is belief. And there is tacit agreement. ’ ‘We may talk about objects. We may talk about attributes of the objects. Or we may talk both about objects and their attributes. ’ This work inspects tacit agreements on assumptions about the relation between objects and their attributes, and studies a way of expressing them, presenting as the result what we term gradual logic in which the sense of truth gradually shifts. It extends classical logic instances with a new logical connective capturing the object-attribute relation. A formal semantics is presented. Decidability is proved. Para-consistent/epistemic/conditional/intensional/description/combined logics are...

  14. Fast Fuzzy C-Means Algorithm Incorporating Convex Combination of Bilateral Filter with Contrast Limited Adaptive Histogram Equalization

    K. Kadambavanama; T. Senthilnathanb
    Fast Generalized Fuzzy c-means clustering algorithm (FGFCM) and its variants are effective methods for image clustering. Even though the incorporation of local spatial information to the objective function reduces their sensitivity to noise to some extent, they are still lack behind in suppressing the effect of noise and outliers on the edges and tiny areas of input image. This article proposes an algorithm to mitigate the disadvantage of FGFCM and its variants and enhances the performance of clustering. The experiments on the synthetic and real images are presented, to exhibit the improvements in the image clustering due to the proposed...

  15. Evolved Reversible Cascades Realized on the CAM-Brain Machine (CBM)

    Andrzej Buller; Marek Perkowski
    This paper presents a method of automated synthesis of reversible cascades in a special cellular automaton called CAM-Brain Machine (CBM). Reversible circuits are investigated because they are expected to dissipate much less energy than their irreversible counterparts. It is believed that one day they will be implemented as nano-scale 3-dimensional chips. A circuit is reversible if the number of its inputs equals the number of its outputs and there is a one-to-one mapping between spaces of input vectors and output vectors. This paper provides (1) a brief introduction to reversible logic concentrating on definitions and properties of the Feynman, Toffoli,...

  16. Creation of Sprites – A New Perspective

    Sheetal Bandekar; Belgaum Karnataka; Vishal Kerkar; Belgaum Karnataka
    In computer graphics the term ‗sprite ‘ is a two dimensional picture that is incorporated into a large scene such as a video game. ‗Pixel art ‘ or ‗Sprite art ‘ deals with creation of sprites. Using the concepts of mathematics especially plane geometry and trigonometry, this research paper gives developers a new logic to create sprites that can be used in a 2D video game to create characters, labels, links, background image, circle and a brick wall. With the proposed latest technology and the new approach towards the creation of sprites a game by name ―SCRAPBOOK ‖ has been...

  17. using Redundant Binary Technique

    L. Sriharish; M. Kamaraju Phd
    The work mainly deals with in improving multiplication process by using Redundant Binary Technique. By implementing the existing method of Multiplication and Accumulation structure in Real time applications, occurs some difficulties like some hard multiples, and getting partial products in multiplication stage, it was not useful for higher radix values. The covalent redundant binary booth encoding algorithm overcomes the hard multiple generation problem and it reduces the partial products. The proposed algorithm dumped into the Booth encoding partial product generation stage. In this stage first step is to change the normal binary to redundant binary to make simple to avoid...

  18. $rec.titulo


    multi-agent systems, machine learning, artificial intelligence, reinforcement learning, optimal control, Q-learning, fuzzy logic, fuzzy reinforcement learning, RoboCup soccer simulation

  19. POLARIZED PSEUDOKRONECKER SYMMETRY AND SYNTHESIS OF x LATTICE DIAGRAMS

    Marek A Perkowski
    Layoutdriven logic synthesis combines logical and physical design to minimize in terconnect length for speed noise and powercritical applications The lattice diagram synthesis approach constructs for combinational functions regular lat tices with only local connections and input buses Lattice diagrams are directly mappable to hardware without additional layout steps This synthesis approach decomposes functions symmetrically using Shannon and Davio expansions and by repeating decomposition variables when necessary It has been proven that lattice diagrams can always be constructed in this manner independent of input variable ordering and expansion types applied Lattice size however is quite sensitive to these parameters This...

  20. Performance Analysis of Full Adder Circuit using Improved Feed through Logic

    Sandeep Sangwan; Jyoti Kedia
    In this paper performance analysis of full adder circuit has been carried out using improved feedthrough logic design technique which is a novel design technique. This technique is an improvement over already existing FTL. The circuit has been designed using existing high speed feedthrough logic and improved feedthrough logic in both 90nm and 180nm technology using cadence tools and a comparison has been done for power and delay. full adder circuit using improved FTL dissipates 37.9 % less than full adder using high speed FTL but delay is increased by 15.13 % but the overall power delay product is reduced...

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