Mostrando recursos 81 - 100 de 10.816

  1. FPGA Architecture for Multi-Style Asynchronous Logic

    Huot , N.; Dubreuil , H.; Fesquet , Laurent; Renaudin , Marc
    Submitted on behalf of EDAA (http://www.edaa.com/)

  2. Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies

    Anghel , L.; Nicolaidis , M.
    In future nanotechnologies failure densities are predicted to be several orders of magnitude higher than in current CMOS technologies. For such failure densities existing fault tolerance implementations are inadequate. This work presents several principles of building multiple-fault tolerant memory cells and logic gates for circuits affected by high defect densities as well as a first evaluation of the area cost and performance.

  3. Cost Reduction and Evaluation of a Temporary Faults Detecting Technique

    Anghel , L.; Nicolaidis , M.
    IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result on unacceptable rates of soft-errors. Furthermore, defect behavior is becoming increasingly complex resulting on increasing number of timing faults that can escape detection by fabrication testing. Thus, fault tolerant techniques will become necessary even for commodity applications. This work considers the implementation and improvements of a new soft error and timing error detecting technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the...

  4. Un nouveau regard sur la machine logique de Jevons

    Amblard , P.
    Jevons's Logic Piano has already been presented in several publications. It was the first hardware devoted to logical inference. In this paper we propose a new view of that machine in the frame of Finite States Machines. Indeed Jevons's Logical Machine is a set of finite states transducers with a Single Instruction Multiple Data organization. This allows it to evaluate some boolean formulas with N variables in space proportional to 2N and in constant time.

  5. Standard-Logic Quasi Delay Insensitive Registers

    Yahya , E.; Renaudin , Marc; Lopin , G.
    International audience

  6. An Effective Approach to Detect Logic Soft Errors in Digital Circuits Based on GRAAL

    Yu , H.; Nicolaidis , M.; Anghel , L.
    ISBN 978-1-4244-2952-3

  7. Measurement of Single Event Transient Pulse Width Induced by Ionizing Radiations in CMOS Combinational Logic

    Perez Ribas , R.; Nicolaidis , M.; Pignol , M.; Bertrand , J.; Belhaddad , H.; Alexandrescu , D.; Leroy , Delphine
    International audience

  8. Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies

    Anghel , L.; Nicolaidis , M.
    ISBN 978-3-540-73006-4

  9. Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies

    Anghel , L.; Nicolaidis , M.
    International audience

  10. Step toward robust and reliable amorphous polymer field-effect transistors and logic functions made by the use of roll to roll compatible printing processes

    Verilhac , J.-M.; Benwadih , M.; Seiler , A.-L.; Jacob , S.; Bory , C.; Bablet , J.; Heitzman , M.; Tallal , J.; Barbut , L.; Frere , P.; Sicard , G.; Gwoziecki , R.; Chartier , Isabelle; Coppard , R.; Serbutoviez , C.
    International audience

  11. Logic circuit protected against transient disturbances

    Nicolaidis , M.
    The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

  12. Electronic circuitry protected against transient disturbances and method for simulating disturbances

    Nicolaidis , M.
    The circuitry comprises successive stages, each comprising a combinatory logic circuit connected to the input of a first latch. Staggered clock signals are respectively associated with the first latches of the odd and even stages. Means for detecting a transient disturbance affecting the first latch of a stage and liable to propagate downstream, compare, in each stage, a value present on the output of the first latch of the stage considered at an observation time with a value present on the input of said first latch at a predetermined observation time taking account of the various propagation times.

  13. BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA

    Rehman , Saif-Ur; Benabdenbi , Mounir; Anghel , L.
    ISBN : 978-1-4799-1583-5

  14. State-aware single event analysis for sequential logic

    Alexandrescu , D.; Evans , A.; Costenaro , E.
    International audience

  15. Designing ultra-low power systems with non-uniform sampling and event-driven logic

    Roa , G.; Le Pelleter , T.; Bonvilain , A.; Chagoya , A.; Fesquet , Laurent
    International audience

  16. Introducción

    Artaud , Hélène
    La presente obra pretende desarrollar un tema que ha dado lugar a importantes debates en estos últimos decenios. La idea de que el mar pueda mantener una relación privilegiada con una sociedad humana, ser objeto de una forma de apropiación singular –tradicional o comunitaria–, que en él se puedan expresar reivindicaciones y fundamen-tar una legitimidad –sobre la base de elementos tan poco normativos como pueden ser las biografías individuales y sus trayectorias, el conocimiento de los topónimos y sus orígenes– es, desde hace poco, objeto de una atención particular. Diversas razones explican, sin duda, la repentina emergencia de la cuestión...

  17. « Una lectura sensible del mar: ecoestesia y toponimia marina de las comunidades de pescadores Imrâgen del Banco de Arguin, Mauritania. »

    Artaud , Hélène
    Una lectura sensible del mar: ecoestesia y toponimia marina de las comunidades de pescadores Imrâgen del banco de Arguin, Mauritania L a parquedad extrema de marcadores materiales en el paisaje atestigua, en países nómadas, una ocupación territorial ajena al régimen de visibilidad e inmutabilidad al que nuestras civilizaciones sedentarias nos tienen acostumbrados. Para los pue-blos nómadas, el paisaje se acompaña de balizas de memoria –tradición oral, sabe-res naturalistas y toponimias–, únicas garantes de su vínculo con el medio natural. Los Imrâgen, como las otras poblaciones nómadas de Mauritania, no constituyen una excepción. Pero a diferencia de estas otras poblaciones, las...

  18. A Dynamic Logic Framework for Abstract Argumentation: Adding and Removing Arguments

    Doutre , Sylvie; Maffre , Faustine; Mcburney , Peter
    International audience

  19. Linear Algebra over a division ring

    Milliet , Cédric
    We consider an analogue of the Zariski topology over a division ring~$\R$ equipped with a ring morphism $\sigma:\R\rightarrow\R$. A basic closed subset of $\R^n$ is given by the zero set of a (finite) family of linear combinations of $\left\{\sigma^{i_1}(x_1),\dots,\sigma^{i_n}(x_n):(i_1,\dots,i_n)\in\mathbb N^n\right\}$ having left coefficients in~$\R$. This enables us to define elementary notions of algebraic geometry: algebraic sets, $\sigma$-morphisms and comorphisms, a notion of Zariski dimension, a notion of radical component of an algebraic set. We classify the algebraic sets over $\R$ up to $\sigma$-isomorphisms when $\sigma$ is onto $\R$ and $[\R:{\rm Fix}(\sigma)]$ infinite (and as a by-product, the additive algebraic groups...

  20. A Timed Graphical Interval Logic

    Dal Zilio , Silvano; Abid , Nouha
    We define a graphical language for expressing timed requirements on concurrent systems. This formal language, called Timed Graphical Interval Logic (TGIL), is inspired by realtime extensions of Dillon's et al Graphical Interval Logic and can be used as an alternative to timed extensions of temporal logic. We define the semantics of TGIL as a set of timed traces—using a dense time semantics—and illustrate its use in formal verification by describing a method for generating an observer from a TGIL specification.

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