
Hung T. Nguyen; Vladik Kreinovich; Valery Shekhter
In science and engineering, there are “paradoxical ” cases when we have some arguments in favor of some statement A (so, the degree to which A is known to be true is positive (nonzero)), and we also have some arguments in favor of its negation ¬A, and we do not have enough information to tell which of these two statements is correct. Traditional fuzzy logic, in which “truth values ” are described by numbers from the interval [0, 1], easily describes such “paradoxical ” situations: the degree a to which the statement A is true and the degree 1 −...

SEQUEL is a newgeneration functional programming language, which allows the specification of types in a notation based on the sequent calculus. The sequent calculus notation suffices for the construction of types for type checking and for the specification of arbitrary logics. Compilation techniques derived from both functional and logic programming are used to derive highperformance ATPs from these specifications. 1

Linh Anh Nguyen
Abstract. Modal logic programming is one of appropriate approaches to deal with reasoning about epistemic states of agents. We specify here the least model semantics, the fixpoint semantics, and an SLDresolution calculus for modal logic programs in the multimodal logic KD4Ig5a, which is intended for reasoning about belief and common belief of agents. We prove that the presented SLDresolution calculus is sound and complete. We also present a formalization of the wise men puzzle using a modal logic program in KD4Ig5a. This shows that it is worth to study modal logic programming for multiagent systems. 1

Nuno Roma; Leonel Sousa; Técnico Inescid
Image moments are used in image analysis for object modelling, matching and representation. The computation of highorder moments is a computational intensive task that can not be implemented in realtime with nowadays generalpurpose processors. This paper proposes a set of specialised processors for generating an image moment of an arbitrary order in real time, by adopting systolic processing techniques and floatingpoint arithmetic units. It proposes a modular and cost effective architecture for generating image moments, with a processing time not dependent on the order of the computed moments. The architecture was implemented using different devices, such as programmable digital processors,...

This paper presents a design approach for implementing a faulttolerant embedded computing node based on the use of lowcost commodity microcontrollers. A combination of software and relatively simple external logic is used to implement faulttolerance in a redundant set of microcontrollers. A node can be protected with different amounts of redundancy (duplex, triplex, hybrid) depending upon the needs of its host subsystem, and is intended to be interconnected with other nodes into a modular distributed network. The structure of the node, and fault detection and recovery algorithms are described, along with a description of an experimental testbed that is being...

Lengning Liu; Mirosław Truszczyński
We study properties of programs with monotone and convex constraints. We extend to these formalisms concepts and results from normal logic programming. They include the notions of strong and uniform equivalence with their characterizations, tight programs and Fages Lemma, program completion and loop formulas. Our results provide an abstract account of properties of some recent extensions of logic programming with aggregates, especially the formalism of lparse programs. They imply a method to compute stable models of lparse programs by means of offtheshelf solvers of pseudoboolean constraints, which is often much faster than the smodels system. 1.

Yuk Wah Wong
Semantic parsing is the construction of a complete, formal, symbolic meaning representation of a sentence. While it is crucial to natural language understanding, the problem of semantic parsing has received relatively little attention from the machine learning community. Recent work on natural language understanding has mainly focused on shallow semantic analysis, such as wordsense disambiguation and semantic role labeling. Semantic parsing, on the other hand, involves deep semantic analysis in which word senses, semantic roles and other components are combined to produce useful meaning representations for a particular application domain (e.g. database query). Prior research in machine learning for semantic...

William M. Fitzgerald; Simon N. Foley Mícheál; Ó Foghlú
Abstract. The provisioning of a firewall is one of the first important steps toward securing access control to a network. However, the effectiveness of a firewall’s access control may be limited or compromised by poor configuration and management of firewall policy decisions. Firewall configuration management involves, either the use of a commandline interface with a deep knowledge requirement of the firewall’s complex lowlevel command syntax, or to a limited extent, the use of a graphical management console. Confidence in a firewall configuration is hampered by the complexity of properly comprehending a configuration that achieves the desired businesslevel security requirements. We...

Timo Latvala; Armin Biere; Keijo Heljanko; Tommi Junttila
Abstract. We consider the problem of bounded model checking for linear temporal logic with past operators (PLTL). PLTL is more attractive as a specification language than linear temporal logic without past operators (LTL) since many specifications are easier to express in PLTL. Although PLTL is not more expressive than LTL, it is exponentially more succinct. Our contribution is a new more efficient encoding of the bounded model checking problem for PLTL based on our previously presented encoding for LTL. The new encoding is linear in the bound. We have implemented the encoding in the NuSMV 2.1 model checking tool and...

Andrew A. Chien; Jay Byun
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase performance. In the Morph/AMRM system, we are exploring the addition of reconfigurable logic, deeply integrated with the processor core, employing the reconfigurability to manage the cache, datapath, and pipeline resources more effectively. However, integration of reconfigurable logic introduces significant protection and safety challenges for multiprocess execution. We analyze the protection structures in a state of the art microprocessor core (R10000), identifying the few critical logic blocks and demonstrating that the majority of the logic in the processor core...

Kenneth Eguro; Kenneth Eguro
Although conventional FPGAs have become indispensable tools due to their versatility and quick design cycles, their logical density, operating frequency and power requirements have limited their use. Domainspecific FPGAs attempt to improve performance over generalpurpose reconfigurable devices by identifying common sets of operations and providing only the necessary flexibility needed for a range of applications. One typical optimization is the replacement of more universal finegrain logic elements with a specialized set of coarsegrain functional units. While this improves computation speed and reduces routing complexity, this also introduces a unique design problem. It is not clear how to simultaneously consider all...

In this paper, we design and formulate a novel trustbased routing protocol for secure transactions, such as military and disaster relief operations, in mobile ad hoc networks (MANETs). The innovative approach is employing the idea of a trust model in the network layer of MANET so as to achieve security in mobile ad hoc networks costeffectively. A salient feature of this approach is that, by establishing formal trust relationships among nodes, computationintensive digital signature authorization and verification are not required for most of the secure transactions in the MANET, and hence the computation cost of the whole network can be...

Matt Kaufmann; J Strother Moore
in this document are those of the author(s) and should not be interpreted as representing the official policies, either expressed or implied, of Computational Logic, Inc., the

Giovanni Conforti; Damiano Macedonio; Vladimiro Sassone
Aiming at a unified view of the logics describing spatial structures, we introduce a general framework, BiLog, whose formulae characterise monoidal categories. As a first instance of the framework we consider bigraphs, which are emerging as a an interesting (meta)model for spatial structures and distributed calculi. Since bigraphs are built orthogonally on two structures, a hierarchical place graph for locations and a link (hyper)graph for connections, we obtain a logic that is a natural composition of other two instances of BiLog: a Place Graph Logic and a Link Graph Logic. We prove that these instances generalise the spatial logics for...

Dominic Hughes
A cornerstone of the theory of proof nets for unitfree multiplicative linear logic (MLL) is the abstract representation of cutfree proofs modulo inessential commutations of rules. The only known extension to additives, based on monomial weights, fails to preserve this key feature: a host of cutfree monomial proof nets can correspond to the same cutfree proof. Thus the problem of finding a satisfactory notion of proof net for unitfree multiplicativeadditive linear logic (MALL) has remained open since the inception of linear logic in 1986. We present a new definition of MALL proof net which remains faithful to the cornerstone of...

H. Andreka, et al.
The aim of our paper is to show that a general theory of Intelligent Systems /IS/ can be based on the mathematical logic and on its model theory. A descriptive defi nition of IS is given. One can see that the investigation of some important as pects of IS's functioning lead us to realize the necessity of a general language concept. The definition of the language is given as a triple: language = <syntax, set of possible worlds, validity>. The usefulness of this language concept for describing the IS functioning is shown. Mathematical background of this concept gives the possibility...

William Da Silva Vianna; Guerold S. Bobrovnitchii
The process o synthesis and sinterization of industrial diamonds is performed under high pressure and temperatures (HPHT) up to 8,0 GPa and 1800ºC in high pressure apparatus (HPA) capable of sustaining these values for determined periods of time using special hydraulic clasps. In order to obtain productive and adequate synthetic diamonds it is necessary to maintain the process parameters (pressure, temperature and time) at a set region of the equation diagram of the carbon phase. One should also consider different variables that involve the system, such as: type of HPA and its refrigeration, type of material of the anvil and...

Prasanna Thati; Grigore Ro
1 Introduction Runtime verification and monitoring have been proposed as lightweight formal verification methods [13] with the explicit goal of checking systems against their formal requirements while they execute. In most monitoring applications, execution traces are available only incrementally and they are much larger than the formulae against which they are checked. Storing an entire execution trace and then performing the formal analysis by having random access to the trace is very expensive and sometimes even impossible. For example, the monitor may lack resources, e.g., if it runs within an embedded system, or the monitor may be expected to react...

This paper provides a case study that shows how a demanding application stresses the capabilities of today’s CAD tools, especially in the integration of products from multiple vendors. We relate our experiences in the design of a large, highspeed multiprocessor computer, using state of the art CAD tools. All logic circuitry is targeted to fieldprogrammable devices (FPDs). This choice amplifies the difficulties associated with achieving a highspeed design, and places extra requirements on the CAD tools. Two main CAD systems are discussed in the paper: Cadence Logic Workbench (LWB) is employed for boardlevel design, and Altera MAX+plusII is used for...

Mark Grechanik
Abstract. Two or more components (e.g., objects, modules, or programs) interoperate when they exchange data, such as XML data. Currently, there is no approach that can detect a situation at compile time when one component modifies XML data so that it becomes incompatible for use by other components, delaying discovery of errors to runtime. Our solution, a Verifier for Interoperating cOmponents for finding Logic fAults (Viola) builds abstract programs from the source code of components that exchange XML data. Viola symbolically executes these abstract programs thereby obtaining approximate specifications of the data that would be output by these components. The...