101.
Topologies, Migration Rates, and Multi-Population Parallel Genetic Algorithms
This paper presents an analysis of parallel genetic algorithms (GAs) with multiple populations
(demes). The analysis makes explicit the relation between the probability of reaching a
desired solution with the deme size, the migration rate, and the degree of the connectivity graph.
The analysis considers arbitrary topologies with a fixed number of neighbors per deme. The
demes evolve in isolation until each converges to a unique solution. Then, the demes exchange
an arbitrary number of individuals and restart their execution. An accurate deme-sizing equation
is derived, and it is used to determine the optimal configuration of an arbitrary number of
demes that minimizes the execution time of...
102.
Network Topologies for Scalable Multi-User Virtual Environments
- Thomas A. Funkhouser
This paper investigates trade-offs of different network
topologies and messaging protocols for multi-uservirtual
environment systems. We present message distribution
techniques appropriate for constructing scalable
multi-user systems for a variety of network characteristics.
Hierarchical system designs utilizing servers
that manage message distribution for entities in separate
regions of a virtual environment are described that
scale to arbitrary numbers of simultaneous users. Experimental
results show that the rate of messages processed
by server workstations in this system design are
less than using previously described approaches.
1. Introduction
With the recent increases in network bandwidth
and graphics performance in desktop computers, there
is a growing interest in distributed visual simulation
systems that allow multiple users to interact in a
shared...
103.
Topologies, Migration Rates, and Multi-Population Parallel Genetic Algorithms
This paper presents a study of parallel genetic algorithms (GAs) with multiple populations (also called demes or islands). The study makes explicit the relation between the probability of reaching a desired solution with the deme size, the migration rate, and the degree of the connectivity graph. The paper considers arbitrary topologies with a fixed number of neighbors per deme. The demes evolve in isolation until each converges to a unique solution. Then, the demes exchange an arbitrary number of individuals and restart their execution. An accurate deme-sizing equation is derived, and it is used to determine the optimal configuration of...
104.
On the semantics of Internet topologies
- Milena Mihail,Christos Gkantsidis,Amin Saberi,Ellen Zegura
Models for network topology are necessary for simulation-based studies of a variety of networking problems. Increasingly the research community is interested in problems that arise due to the large scale of the Internet (e.g., BGP routing, performance of peer-to-peer systems). For these sorts of problems, the potential to model the fullscale AS-level topology is appealing. To date, the most successful approach to modeling the AS-level topology is the degree-driven approach of Inet. Inet predicts the degrees of the topology by extrapolation from available data, then constructs a topology meeting the degree sequence using a preferential connectivity heuristic. We focus on...
105.
Mesh Routing Topologies For FPGA Arrays
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing
devices, and software accelerators. An important part of designing such a system is determining the proper
routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and
delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been
proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and
propose several constructs for more efficient topologies. These reduce inter-chip routing costs by more than
50% over the basic 4-way Mesh.
Introduction
In the time since they...
106.
Mesh Routing Topologies for Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing
devices, and software accelerators. An important part of designing such a system is determining the proper
routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and
delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been
proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and
propose several constructs for more efficient topologies. These reduce inter-chip delays by more than 60%
over the basic 4-way Mesh.
Introduction
In the time since they were...
107.
Mesh Routing Topologies For Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of
FPGAs for logic emulators, custom computing devices,
and software accelerators. An important part of designing
such a system is determining the proper routing topology
to use to interconnect the FPGAs. This topology can
have a great effect on the area and delay of the resulting
system. Tree, Bipartite Graph, and Mesh interconnection
schemes have all been proposed for use in FPGA-based
systems. In this paper we examine Mesh interconnection
schemes, and propose several constructs for more efficient
topologies. These reduce inter-chip delays by more than
60% over the basic 4-way Mesh.
Introduction
In the time since they were introduced, FPGAs have
moved from being...
108.
Mesh Routing Topologies For FPGA Arrays
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing
devices, and software accelerators. An important part of designing such a system is determining the proper
routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and
delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been
proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and
propose several constructs for more efficient topologies. These reduce inter-chip routing costs by more than
50% over the basic 4-way Mesh.
Introduction
In the time since they...
109.
Mesh Routing Topologies For FPGA Arrays
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing
devices, and software accelerators. An important part of designing such a system is determining the proper
routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and
delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been
proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and
propose several constructs for more efficient topologies. These reduce inter-chip routing costs by more than
50% over the basic 4-way Mesh.
Introduction
In the time since they...
110.
Mesh Routing Topologies For Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of
FPGAs for logic emulators, custom computing devices,
and software accelerators. An important part of designing
such a system is determining the proper routing topology
to use to interconnect the FPGAs. This topology can
have a great effect on the area and delay of the resulting
system. Tree, Bipartite Graph, and Mesh interconnection
schemes have all been proposed for use in FPGA-based
systems. In this paper we examine Mesh interconnection
schemes, and propose several constructs for more efficient
topologies. These reduce inter-chip delays by more than
60% over the basic 4-way Mesh.
Introduction
In the time since they were introduced, FPGAs have
moved from being...
111.
Mesh Routing Topologies for Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom
computing devices, and software accelerators. An important part of designing such a system is
determining the proper routing topology to use to interconnect the FPGAs. This topology can have a
great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh
interconnection schemes have all been proposed for use in FPGA-based systems. In this paper we
examine Mesh interconnection schemes, and propose several constructs for more efficient topologies.
These reduce inter-chip delays by more than 60% over the basic 4-way Mesh.
Introduction
Field-programmable gate arrays (FPGAs) are devices...
112.
Mesh Routing Topologies For Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of
FPGAs for logic emulators, custom computing devices,
and software accelerators. An important part of designing
such a system is determining the proper routing topology
to use to interconnect the FPGAs. This topology can
have a great effect on the area and delay of the resulting
system. Tree, Bipartite Graph, and Mesh interconnection
schemes have all been proposed for use in FPGA-based
systems. In this paper we examine Mesh interconnection
schemes, and propose several constructs for more efficient
topologies. These reduce inter-chip delays by more than
60% over the basic 4-way Mesh.
Introduction
In the time since they were introduced, FPGAs have
moved from being...
113.
Mesh Routing Topologies For Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing
devices, and software accelerators. An important part of designing such a system is determining the proper
routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and
delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been
proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and
propose several constructs for more efficient topologies. These reduce inter-chip delays by more than 60%
over the basic 4-way Mesh.
Introduction
In the time since they were...
114.
Mesh Routing Topologies For Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing
devices, and software accelerators. An important part of designing such a system is determining the proper
routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and
delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been
proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and
propose several constructs for more efficient topologies. These reduce inter-chip delays by more than 60%
over the basic 4-way Mesh.
Introduction
In the time since they were...
115.
Mesh Routing Topologies For FPGA Arrays
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing
devices, and software accelerators. An important part of designing such a system is determining the proper
routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and
delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been
proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and
propose several constructs for more efficient topologies. These reduce inter-chip routing costs by more than
50% over the basic 4-way Mesh.
Introduction
In the time since they...
116.
Mesh Routing Topologies For Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of
FPGAs for logic emulators, custom computing devices,
and software accelerators. An important part of designing
such a system is determining the proper routing topology
to use to interconnect the FPGAs. This topology can
have a great effect on the area and delay of the resulting
system. Tree, Bipartite Graph, and Mesh interconnection
schemes have all been proposed for use in FPGA-based
systems. In this paper we examine Mesh interconnection
schemes, and propose several constructs for more efficient
topologies. These reduce inter-chip delays by more than
60% over the basic 4-way Mesh.
Introduction
In the time since they were introduced, FPGAs have
moved from being...
117.
Unicast-based Characterization of Network Loss Topologies
- Khaled Harfoush,Azer Bestavros,John Byers
| Current Internet transport protocols
make end-to-end measurements and maintain perconnection
state to regulate the use of shared network
resources. When a number of such connections
share a common endpoint, that endpoint has
the opportunity to correlate these end-to-end measurements
to better diagnose and control the use
of shared resources. A valuable characterization of
such shared resources is the loss topology". From
the perspective of a server with concurrent connections
to multiple clients, the loss topology is a
logical tree rooted at the server in which edges represent
lossy paths between a pair of internal network
nodes. We develop an end-to-end unicast
packet probing technique and an associated analytical
framework to: (1) infer loss topologies,...
118.
Training High-Order Hidden Markov Model Topologies
- J. A. Du Preez,D. M. Weber
We present two powerful tools that allow efficient training of arbitrary- (including mixed and infinite) order hidden
Markov models. The method rests on two parts: an algorithm that can convert high-order models to an equivalent
first-order representation (ORder rEDucing), and a Fast (order) Incremental Training algorithm. We demonstrate that
this method is more flexible, results in significantly faster training and improved generalisation compared to prior work.
Using this, we develop special mixed-order topologies that distinguishes between the context- and duration modelling
capabilities of high-order HMMs. These techniques are extensively tested and demonstrated on synthetic data as well as
a real world (automatic language recognition) problem.
Keywords: high...
119.
Mesh Routing Topologies For FPGA Arrays
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing
devices, and software accelerators. An important part of designing such a system is determining the proper
routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and
delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been
proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and
propose several constructs for more efficient topologies. These reduce inter-chip routing costs by more than
50% over the basic 4-way Mesh.
Introduction
In the time since they...
120.
Mesh Routing Topologies for Multi-FPGA Systems
- Scott Hauck,Gaetano Borriello,Carl Ebeling
There is currently great interest in using fixed arrays of
FPGAs for logic emulators, custom computing devices, and
software accelerators. An important part of designing such
a system is determining the proper routing topology to use
to interconnect the FPGAs. This topology can have a great
effect on the area and delay of the resulting system.
Crossbar, Hierarchical Crossbar, and Mesh interconnection
schemes have all been proposed for use in FPGA-based
systems. In this paper we examine Mesh interconnection
schemes, and propose several constructs for more efficient
topologies. These reduce inter-chip delays by more than
60% over the basic 4-way Mesh.
Introduction
Field-programmable gate arrays (FPGAs) are devices that
can be programmed and reprogrammed...
