1. A Parallel Band-Matrix Solver for a Circuit Simulation Problem - Luís Miguel Silveira; Lu'is Miguel Silveira
This report sumarizes and evaluates an implementation of a general band-matrix solver algorithm on a massively parallel multiprocessor, the "Connection Machine". The band algorithm is used in a nonlinear relaxation-based circuit simulator for solving the system of equations associated with the node voltages, at each Newton iteration at each time step. Acknowledgments This report is part of the requisites for course 18.435/6.848, taught by Prof. F. Thomson Leighton at the Massachusetts Institute of Technology in the Fall Term of 1988. I thank Andrew Lumsdaine who wrote the original sequential version of the simulator and did most of the circuit element...

2. Puertos locales y bienes de consumo: importación de mercancías finas en Santander, Colombia, 1870-1900 - Carreño Tarazona, Clara Inés
Este artículo analiza la importación de bienes de consumo, el medio social y los puertos locales, así como elementos que formaron parte del circuito mercantil en Santander, Colombia, entre 1870 y 1900. En primer lugar se examina el movimiento comercial realizado entre los principales puertos extranjeros y los puertos locales colombianos. En segundo lugar se estudian las diversas formas de asociación, adoptadas por los principales importadores para incursionar en el comercio exterior. Finalmente, se indican los bienes y mercancías de lujo, introducidas por dichos importadores, y su incorporación en los diferentes grupos sociales. Las fuentes empleadas son los protocolos notariales,...

3. HIGH PULSE AND AVERAGE POWER LOW-INDUCTION LOAD
A high pulse and average power low-induction load with a built-in divider is described in this report. The load has a nominal resistance of 25 Ohm and is designed to operate with a repetition rate of up to 50 Hz at the pulse duration (FWHM) of 100 ns, at the rise/fall time of 50 ns and pulse amplitude of up to 40 kV. In this mode the dissipated energy is equal to about 6.4 J per pulse and average power is equal up to 320 W. There is no heat removing from the load resistant layer during one pulse practically...

4. A rational formulation of thermal circuit models for electrothermal simulation. Part I: finite element method - Jia Tzer Hsu; Loc Vu-quoc
Abstract- As the size of the semiconductor devices is getting smaller with advanced technology, self-heating effects in power semiconductor devices are becoming important. An electrother-mal simulation of complete power electronic systems that include Si chips, thermal packages, and heat sinks is essential for an accurate analysis of the behavior of these systems. This paper presents a rational approach to construct thermal circuit net-works equivalent to a discretization of the heat equation by the finite element method. Elemental thermal circuit networks are developed, which correspond to the linear and cubic Hermite elements in the 1-D case, to the triangular and rectangular...

5. Simple way of teaching transistor amplifiers - Bogdan M. Wilamowski
For small signal analysis a simple change from commonly used tranconductance gm to transresistance rm=1/gm leads to a significant simplification of all equations. Moreover these equations are much easier to memorize since they have a form of resistor ratio for CE (CS) and CB (CG) configurations and the form or resistor divider for CC (CD) configuration. With presented approach most of students are able to read diagrams and to understand the effect of each element change on the circuit performance. Students are not lost with messy equations, but they are in control of their design and they know which parameters...

6. How to efficiently capture on-chip inductance effects: introducing a new circuit element K - Anirudh Devgan; Hao Ji; Wayne Dai
On-chip inductance extraction and analysis is becom-ing increasing critical. Inductance extraction can be diffi-cult, cumbersome and impractical on large designs as in-ductance depends on the current return path — which is typically unknown prior to extracting and simulating the circuit model. In this paper, we propose a new circuit ele-ment, K, to model inductance effects, at the same time be-ing easier to extract and analyze. K is defined as inverse of partial inductance matrix L, and has locality and sparsity normally associated with a capacitance matrix. We pro-pose to capture inductance effects by directly extracting and simulating K, instead of...

7. Generating Reduced Order Models via PEEC for Capturing Skin and Proximity Effects - Mattan Kamon; Nuno Marques; L. Miguel Silveira; Jacob White
In the past, model order reduction techniques have been successfully employed for 3-D PEEC interconnect models. This paper explores the difficulties in generating low order models when PEEC-like models include volume filaments to accurately capture skin and proximity effects. 1 Introduction The Partial Element Equivalent Circuit (PEEC) technique has long been used to model three dimensional interconnect structures [1]. In order to simulate the interaction of the interconnect with nonlinear circuit devices such as drivers and receivers, the PEEC model must somehow be incorporated into a time domain circuit simulator such as SPICE. However, inclusion of the PEEC model directly...

8. The Best Approximation of the Field Effects in Electric Circuit Coupled Problems - Daniel Ioan; Irina Munteanu; Irina Munteanu (ieee Members; Cristian-george Constantin
The paper presents a new efficient technique to solve electromagnetic field problems coupled with electric or electronic circuits. It is based on a post-processing algorithm which extracts from the numerical field solution a lumped parameters circuit with imposed complexity, ensuring minimal approximation error. In order to evaluate the algorithm's accuracy a general theory regarding equivalent circuits for quasistationary field effects was developed. The new technique was applied and errors were evaluated in two simple but relevant cases. A practical application (the FLUXSET sensor modeling) is also presented. Index terms---Eddy currents, distributed parameter circuits, approximation methods, identification, magnetic circuits, magnetic field...

9. A Hybrid Element Method For Capacitance Extraction In Vlsi Layout Verification System - E.B. Nowacka; N.P. van der Meijs; N. P. Vd. Meijs
In this paper we describe a hybrid element method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC's). We present a stand-alone extraction program which we developed for validation and testing purposes. We show that the hybrid method can be included in our VLSI layout verification package Space. 1 Introduction Parasitic interconnect capacitances in integrated circuits (IC's) are playing an increasingly significant role in the circuit's performance. Therefore, designers of modern IC's...

10. INVESTIGATIONS ON THE DYNAMICS OF A METAL-FERROELECTRIC- SEMICONDUCTOR HETEROSTRUCTURE - B. Mereu; M. Alexe; M. Diestelhorsta; C. P. Cristescub; C. Stanb
A series RLC electric circuit with the metal-ferroelectric-semiconductor (MFS) hetero-structure playing the role of nonlinear capacity shows various nonlinear dynamics such as period doubling and Ruelle-Takens scenarios of evolution to chaos. In this paper we present preliminary experimental investigations and theoretical analysis on the dynamics of this structure. We focus only on a period-doubling bifurcation evolution to chaos induced by the change in the amplitude of a sinusoidal driving. A theoretical model of MFS structure as nonlinear element of an electrical circuit justifies a model of two coupled nonlinear Duffing oscillators. The model takes into consideration the presence of two...

11. Floating-Gate MOS Synapse Transistors - Diorio, Chris; Hasler, Paul; Minch, Bradley A.; Mead, Carver
Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices, such as EEPROM transistors. typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floating-gate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through Si0_2, these devices have not seen wide use as memory elements in silicon learning systems.

12. IMPEDANCIA BIO-ELÉCTRICA COMO TÉCNICA NO-DESTRUCTIVA PARA MEDIR LA FIRMEZA DE LA FRESA (Fragaria x ananassa Duch) Y SU RELACIÓN CON TÉCNICAS CONVENCIONALES - GONZÁLEZ ARAIZA, JOSÉ RAYMUNDO
La técnica de impedancia bio-eléctrica permite la caracterización de sistemas biológicos mediante la aplicación de una corriente eléctrica en un rango de frecuencias determinado, logrando así la observación del comportamiento de las propiedades eléctricas, parámetros que están relacionados con la estructura y composición del material. Asimismo, el análisis de la impedancia bio-eléctrica, aplicada a los materiales biológicos, proporciona información acerca de los cambios fisiológicos dentro y fuera de la célula, así como de las membranas y los tejidos. Esta técnica tiene la ventaja de ser simple y no destructiva. Algunos estudios relacionados con esta propiedad se han llevado a cabo...

13. Caracterización y cálculo del circuito equivalente de un motor de inducción desde la placa de características - Pineda Sánchez, Manuel
En este artículo se expone la forma de leer la placa de características, y se relaciona los diferentes parámetros que en esta placa con los elementos del circuito equivalente. La placa de características tiene datos de diferentes variables, tanto constructivos como de índole mecánica o térmica. Se plantea en este trabajo la forma de identificarlos, e incluso se les instruye en la variabilidad normativa de estos parámetros. Se presentan también en este trabajo las diferentes aplicaciones que puede tener una misma máquina eléctrica según pueda utilizarse en Europa o en América, y como un mismo motor puede tener comportamiento diferentes según su...

14. Significado y medida de los fenómenos de desfase en los sistemas trifásicos desequilibrados, lineales. Aplicación a la medida en sistemas con conductor neutro - GRAÑA LÓPEZ, MANUEL ÁNGEL
La tesis doctoral, cuyo título se indica más arriba, está dedicada al estudio y medida de los fenómenos reactivos en los sistemas eléctricos trifásicos. La tesis se ha estructurado en 6 Capítulos y la Bibliografía. En el Capítulo se han analizado críticamente las definiciones de potencia reactiva establecidas por las principales teorías de la potencia eléctrica, desde finales del siglo XIX hasta nuestros días. En el Capítulo II, se han analizado los fenómenos reactivos, o de desfase, entendidos para las tensiones y corrientes de secuencia directa y frecuencia fundamental, tal como establece la teoría Unificadora y la IEEE Standard 1459-2000, en base...

15. Microondas. Síntesis de redes de 2 accesos mediante circuitos equivalentes con elementos concentrados - Baquero Escudero, Mariano
En este objeto de aprendizaje se estudia como encontrar el circuito equivalente con componentes concentrados de una red de dos acceos a partir del conocimiento de las matrices de impedancia y admitancia.

16. Corriente transitoria en un circuito RL serie con excitación C.C. + C.A. - Martínez Román, Javier Andrés
Cálculo de la corriente transitoria en un circuito RL alimentado por tensión alterna + continua y representación junto con la tensión de alimentación (Magenta) y en los elementos R (Rojo) y L(Azul) del circuito.

17. Corriente transitoria en un circuito RC serie con excitación C.C. + C.A. - Martínez Román, Javier Andrés
Cálculo de la corriente instantánea y representación junto con la tensión de alimentación (Magenta) y en los elementos R (Rojo) y C(Azul) del circuito.

18. Clock Period Minimization of Semi-Synchronous circuits by Gate-Level Delay Insertion - Tomoyuki Yoda; Atsushi Takahashi; Yoji Kajitani
A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not nec-essarily simultaneously. A feature of semi-synchronous circuits is that the minimum delay between registers may be critical with respect to the clock period of the circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The max-imum delay-to-register ratio of the cycles on the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous frame-work by the proposed gate-level delay insertion method on the assumption that...

19. Electronically tunable multi-terminal floating nullor and its application - Worapong Tangsrirat
Abstract. A realization scheme of an electronically tun-able multi-terminal floating nullor (ET-MTFN) is de-scribed in this paper. The proposed circuit mainly employs a transconductance amplifier, an improved translinear cell, two complementary current mirrors with variable current gain and improved Wilson current mirrors, which provide an electronic tuning of the current gain. The va-lidity of the performance of the scheme is verified through PSPICE simulation results. Example applications employing the proposed ET-MTFN as an active element demonstrate that the circuit properties can be varied by electronic means.

20. Extraction of Coupled RLC Network from Multi-level Interconnects for Full Chip Simulation - S. Yoon; T. Won
In this paper, an approach is proposed for extracting coupled RLC network from multi-level interconnects. The proposed approach starts with a step of partitioning the layout of the full-chip under consideration into several sub-layouts, followed by steps of fracturing the partitioned layout and transforming into the three-dimensional structure. The layout is then classified into three species of segments, i.e. electrical node segments, resistive segments, capacitive segments, in order to generate a coupled RLC network from the layout data. These segments are employed for specifying the simulation domain and the boundary condition. Finally, the parasitics are calculated by a finite element...

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