Specification of multiple AUV strategies for search of freshwater oceanic sources - Eduardo Silva; Alfredo Manuel Martins; J. Almeida; João Tasso Sousa; Fernando Lobo Pereira
System and mission requirements for the use of Autonomous Underwater Vehicles (AUV) were defined. A requirement analysis was done having in mind the definition of search methodologies involving multiple cooperating vehicles. Control and navigation issues were addressed. Various search strategies were proposed and analyzed in terms of control, navigation and overall system requirements.
Low-Power In-Circuit Testing of a LNA - José Machado da Silva
A new technique is proposed to tackle in-circuit testing of embedded RF blocks. It relies on observing the cross-correlation between its output voltage and power supply current, using a translinear cross-correlator circuit. Although a structural test is performed, simulation results show that fault detection criteria can be established based on acceptable deviations of performance characterization parameters. The case of a Low Noise Amplifier is presented.
Design for Embedded Testing of an LNA - José Machado da Silva; António Pinho; José Silva Matos
In-circuit testing methodologies are required to tackle the evaluation of embedded radio-frequency circuits. This paper presents design considerations for the test circuitry proposed to implement a methodology for on-chip testing a low-noise amplifier.
A previously reported test technique consists on applying to the LNA a sequence of stimuli with different amplitudes, and on measuring the output amplitude for each input level. The obtained set of coordinates (Vin, Vout) allows finding the 3rd order polynomial that best fits the LNA’s transfer function. The LNA input voltages which lead to the 1dB compression (P1dB) and third-order intercept (IP3) points are then calculated...
A High Level Test Processor and Test Program Generator - Francisco Duarte; José Carlos Alves; José Machado da Silva; António Pinho; José Silva Matos
Embedded test within integrated systems allows to overcome some of the difficulties found when testing using only an external tester. The reutilization of a reconfigurable FPGA-like block that may exist in certain SoC systems, enables the implementation of on-chip test processors highly optimized to meet the specific requirements of the test procedure for each block. The fast reconfiguration of SRAM-based FPGA blocks allows sharing the same physical area among the set of different circuits that may be necessary to implement the on-chip test suite of the whole system.
This paper addresses the high level generation of specific programmable processors for...
A Low-Power Oscillation Based LNA BIST Scheme - José Machado da Silva
Abstract—Test stimuli generation and power consumption are
two issues that jeopardize the design of built-in self test schemes.
The LNA testing approach presented herein relies on converting the
amplifier into an oscillator and on using a low-power correlator to
obtain a signature from the cross-correlation between the dynamic
power supply current and the LNA’s output voltage. In test mode a
high fault coverage is obtained together with a low power consumption,
while avoiding an extra stimulus generator. No significant performance
degradation results from the added test circuitry. Concerning the
interface with the external tester, a digital signal is required to switch
between normal and test modes, as well as a...
A Processor for Testing Mixed-Signal Cores in System-on-Chip - Francisco Duarte; José Machado da Silva; José Carlos Alves; António Pinho; José Silva Matos
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.