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Nomenclatura Unesco > (33) Ciencias Tecnológicas

Mostrando recursos 121 - 140 de 2,130

121. On a Solution Concept to Impulsive Differential Systems - Tatiana Filippova; F. Lobo Pereira

122. Second‐order Necessary Conditions of Optimality for Abnormal Solutions of Nonlinear Problems with Equality and Inequality Constraints - Aram Arutyunov; Dmitry Karamzin; Fernando Lobo Pereira

123. Coordination Strategies between UAV and AUVs for Ocean Exploration - Sujit Baliyarasimhuni; João B. Sousa; F. Lobo Pereira

124. Vision-based Autonomous Surface Vehicle Docking Manoeuvre - A. A. Martins; J.Almeida; A. F. Silva; F. Lobo Pereira

125. Operations and control of unmanned underwater vehicles - Márcio Correia; Paulo Sousa Dias; Sérgio Fraga; Rui Gomes; Rui Gonçalves; L. Madureira; F. Lobo Pereira; José Queirós Pinto; António Nogueira Santos; Alexandre Arada de Sousa; João B. Sousa

126. Neptus – A Framework to Support Multiple Vehicle Operations - Paulo Sousa Dias; Rui Gomes; José Queirós Pinto; Sérgio Fraga; Gil Manuel Gonçalves; J. Borges de Sousa; F. Lobo Pereira

127. Low-Power In-Circuit Testing of a LNA - José Machado da Silva
A new technique is proposed to tackle in-circuit testing of embedded RF blocks. It relies on observing the cross-correlation between its output voltage and power supply current, using a translinear cross-correlator circuit. Although a structural test is performed, simulation results show that fault detection criteria can be established based on acceptable deviations of performance characterization parameters. The case of a Low Noise Amplifier is presented.

128. Design for Embedded Testing of an LNA - José Machado da Silva; António Pinho; José Silva Matos
In-circuit testing methodologies are required to tackle the evaluation of embedded radio-frequency circuits. This paper presents design considerations for the test circuitry proposed to implement a methodology for on-chip testing a low-noise amplifier. A previously reported test technique consists on applying to the LNA a sequence of stimuli with different amplitudes, and on measuring the output amplitude for each input level. The obtained set of coordinates (Vin, Vout) allows finding the 3rd order polynomial that best fits the LNA’s transfer function. The LNA input voltages which lead to the 1dB compression (P1dB) and third-order intercept (IP3) points are then calculated...

129. A High Level Test Processor and Test Program Generator - Francisco Duarte; José Carlos Alves; José Machado da Silva; António Pinho; José Silva Matos
Embedded test within integrated systems allows to overcome some of the difficulties found when testing using only an external tester. The reutilization of a reconfigurable FPGA-like block that may exist in certain SoC systems, enables the implementation of on-chip test processors highly optimized to meet the specific requirements of the test procedure for each block. The fast reconfiguration of SRAM-based FPGA blocks allows sharing the same physical area among the set of different circuits that may be necessary to implement the on-chip test suite of the whole system. This paper addresses the high level generation of specific programmable processors for...

130. A Low-Power Oscillation Based LNA BIST Scheme - José Machado da Silva
Abstract—Test stimuli generation and power consumption are two issues that jeopardize the design of built-in self test schemes. The LNA testing approach presented herein relies on converting the amplifier into an oscillator and on using a low-power correlator to obtain a signature from the cross-correlation between the dynamic power supply current and the LNA’s output voltage. In test mode a high fault coverage is obtained together with a low power consumption, while avoiding an extra stimulus generator. No significant performance degradation results from the added test circuitry. Concerning the interface with the external tester, a digital signal is required to switch between normal and test modes, as well as a...

131. A Processor for Testing Mixed-Signal Cores in System-on-Chip - Francisco Duarte; José Machado da Silva; José Carlos Alves; António Pinho; José Silva Matos
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.

132. Visita a la Unidad de Recursos de Información Científica para la Investigación (URICI) de personal bibliotecario del Consejo Nacional de Ciencia y Tecnología de México (CONACYT) - Cottereau, Mario
El 28 de noviembre la URICI recibió la visita de un grupo de bibliotecarios y personal académico perteneciente al Consejo Nacional de Ciencia y Tecnología de México (CONACYT), organismo que abarca 27 instituciones de investigación que cubren los principales campos del conocimiento científico y tecnológico, agrupados en tres áreas: Desarrollo Tecnológico, Ciencias Exactas y Naturales y Ciencias Sociales y Humanidades. El CONACYT es una institución con grandes semejanzas con el CSIC por su estructura administrativa e implantación geográfica en todo el país.

133. Uma Meta-Heurística para o Problema da Programação de Projectos com Recursos Limitados - Mendes, J.J.M; Gonçalves, J. F.

134. Descoberta da topologia do sistema na ausência de sinais com redes neurais autoassociativas - Jakov Krstulovic; Vladimiro Miranda; Hrvoje Keko; Jorge Pereira

135. A comparative study of greywater from domestic and public buildings - Cristina Santos; Cristina Matos; Francisco Taveira Pinto

136. Classifier-based Cell Segmentation from Confocal Microscopy Images - Mónica Marcuzzo; Pedro Quelhas; Ana Campilho; Ana Maria Mendonça; Aurélio Campilho

137. Robust optical flow estimation - Sánchez Pérez, Javier; Monzón López, Nelson; Salgado de la Nuez, Agustín Javier
[EN] In this work, we describe an implementation of the variational method proposed by Brox et al. in 2004, which yields accurate optical flows with low running times. It has several benefits with respect to the method of Horn and Schunck: it is more robust to the presence of outliers, produces piecewise-smooth flow fields and can cope with constant brightness changes. This method relies on the brightness and gradient constancy assumptions, using the information of the image intensities and the image gradients to find correspondences. It also generalizes the use of continuous L1 functionals, which help mitigate the efect of...

138. A variational approach to camera motion smoothing - Álvarez León, Luis Miguel; Gómez Déniz, Luis; Henríquez Castellano, Pedro; Mazorra Manrique de Lara, Luis
[EN] In this paper we study a variational problem derived from a computer vision application: video camera calibration with smoothing constraint. By video camera calibration we meanto estimate the location, orientation and lens zoom-setting of the camera for each video frame taking into account image visible features. To simplify the problem we assume that the camera is mounted on a tripod, in such case, for each frame captured at time t , the calibration is provided by 3 parameters : (1) P(t) (PAN) which represents the tripod vertical axis rotation, (2) T(t) (TILT) which represents the tripod horizontal axis rotation...

139. List Scheduling Algorithm for Heterogeneous Systems by an Optimistic Cost Table - Hamid Arabnejad; Jorge Manuel Gomes Barbosa
Efficient application scheduling algorithms are important for obtaining high performance in heterogeneous computing systems. In this paper, we present a novel list-based scheduling algorithm called Predict Earliest Finish Time (PEFT) for heterogeneous computing systems. The algorithm has the same time complexity as the state-of-the-art algorithm for the same purpose, that is, O(v^2.p) for v tasks and p processors, but offers significant makespan improvements by introducing a look-ahead feature without increasing the time complexity associated with computation of an Optimistic Cost Table (OCT). The calculated value is an optimistic cost because processor availability is not considered in the computation. Our algorithm is only based on an OCT...

140. Engineering intervention management using a probabilistic methodology for hot spot identification - Sara Ferreira; António Fidalgo Couto
A theoretical definition of a hotspot is any location that has a higher expected number of accidents than other similar locations as a result of local risk factors present at the location. This study presents an alternative approach to research regarding hot spot definition and identification based on a probabilistic model that defines the dependent variable as an indicator of a discrete choice. A binary choice model was used considering a binary dependent variable that differentiates a hot spot (category 1) from a safe (category 0) site set by the number of accidents per kilometer. To define these two categories,...

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